1. Field of the Invention
The present invention relates to a semiconductor device to allow high breakdown voltage in semiconductor elements formed in an element region of island configuration, and a method of fabricating same. The semiconductor device according to the present invention can be applied in an IC for drive use having a plurality of high-voltage output stages employed for example in a flat-panel display, and in particular an electroluminescence (EL) display or the like.
2. Related Arts
Conventionally, as shown in FIG. 7, a device which forms a thick oxide film 20 (LOCOS oxide film) between a gate and drain to alleviate an electric field between the gate and drain exists as a device to cause the breakdown voltage of an element in an MOS transistor to increase.
FIG. 8 indicates a case where this device has a SOI (silicon on insulator) structure, i.e., an element structure of isolating type. Herein, when a high voltage of positive polarity is applied to a drain side of an n-channel MOS transistor, equipotential lines expand and an electric-field-alleviating effect due to a buried oxide film 21 appears, as indicated in the right-hand portion of the drawing; In contrast to the left-hand portion of the drawing in which high voltage of negative polarity is applied to a source side, equipotential lines become dense and an electric field is concentrated at a pn-junction interface proximately to the source due to a relationship of potential differential with a Si substrate 22, and a problem occurs in which required breakdown voltage cannot be obtained.
Additionally, a device which disposes an electric-field-alleviating layer of low concentration (but of higher concentration than the SOI layer thereabove) below an SOI layer has been disclosed in Japanese Patent Application Laid-open No. 1-103851 Patent Gazette as electric-field alleviation of this type. Namely, according to this device, a portion of the voltage applied to an element is effectively allotted to a buried oxide film by causing a portion of high voltage of reversed direction to be allotted to the electric-field-alleviating layer, so as to achieve high breakdown voltage.
When this device is applied in the above-described structure, as shown in FIG. 9, the electric field is alleviated by widening the depletion layer in the electric-field-alleviating layer 23. Thus, the electric field concentration at the pn-junction interface proximate to the source is eliminated, and the required breakdown voltage can be obtained, even where a high voltage of negative polarity is applied to the source side.
However, it is necessary to form the electric-field-alleviating layer 23 with a conductivity type opposite the n.sup.- layer thereabove. This is because if it were made to be of the same conductivity type, the structure would be similar to the device depicted in FIG. 8, and there would be no widening of the depletion layer at the electric-field-alleviating layer 23, thus failing to achieve the desired electric-field-alleviating effect. Consequently, a restriction is created in that a p-type electric-field-alleviating layer must be provided in an n-channel MOS transistor, and that an n-type electric-field-alleviating layer must be provided in a p-channel MOS transistor.
However, where it is necessary to form n-channel MOS transistors and p-channel MOS transistors on the same semiconductor substrate, a problem occurs in that different electric-field-alleviating layers must be provided in each of these element regions, due to this restriction.